Senior ASIC/FPGA Verification Engineer - XD-RDC-007

The Role

  • Responsible for creating test bench specifications and test plans
  • Responsible for implementing test platform according to specifications;
  • Responsible for understanding RTL design, creating directional and random testing (Verilog or C) to achieve high coverage;
  • Responsible for verifying the effectiveness of RTL in simulation, gate level simulation and ASIC/FPGA;
  • Complete other temporary work arranged by the superior.

Required Qualifications

  • Have experience in verifying and debugging high speed interface (USB, DDR) and network protocol (Ethernet) on ASIC/FPGA;
  • Have experience in verifying and debugging multi-processor AXI interconnect ASIC/FGPA system;
  • Familiar with MAC or baseband verification process is preferred;
  • Have experience in software and hardware integration with software engineers
  • Have the expertise of PERL, Make file and system Verilog, and can automatically generate and check tests;
  • Familiarity with random constraints and system Verilog structures, such as arrays, queues and classes;

Desired Qualifications

  • Strong system Verilog programming skills, including top-level and unit level validation.
  • More than 5 years of ASIC/FPGA validation experience or SOC and MAC/ baseband module test bench creation experience


  • Undergraduate.