Our WAVE™ Reconfigurable Hardware architecture is revolutionizing baseband ASIC design, supporting multiple standards and combining communications protocol processing and edge computing all in a single chip with the performance of hardware and the flexibility of software.


One Chip. Multi Standard. Multi Band.

Taking advantage of convergence of communications standards and ecosystems, the Siliconwaves SoC employs a breakthrough architecture to support major standards in 5G and Wi-Fi all within a single baseband processor with reconfigurable hardware modules. The end result is a powerful single chip, multi-standard SoC with similar area and power consumption as a single-standard chip, but with much more flexibility and major performance enhancement in cross-standard connectivity applications common in today’s environment. Combined with proven RF solutions, the baseband SoC will support all major spectrum bands around world.

One Chip. Communicate. Compute.

With cluster processor cores, the flexible SoC not only support communications protocol processing but also edge computing whenever needed. Putting compute resources available where connectivity is, allows shortest response time possible, moving data center capabilities of storage, analytics and automation to the edge. With native support for 5G MEC and a simple and flexible software API, the SoC offers a foundation for distributed cloud implementation by making resources available wherever needed (whether its a cell site, a central office, an aggregation site, a metro data center or customer premises) and on any connected devices.


An entire new approach to chip architecture.

We have taken an entire new architecture approach to baseband SoC design with parameterized and time shared hardware modules orchestrated through a powerful software API layer resulting in a breakthrough SoC platform with software-like flexibility and hardware-like performance. Key hardware modules are fully parameterized to support different standards, orchestrated through software API and time shared by different processing threads. System capabilities like number of simultaneous users, MIMO chains, channel aggregation, and aggregated throughput can be scaled linearly by interconnecting the SoCs together at the system level.